2023 | ||
 | A contactless transceiver operating employs a dual-edge tracking clock and data recovery loop for applications like giant video walls. It achieves error-free communication up to a 3 mm air-gap distance using capacitive coupling. M. B. Younis et al., "A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2. | |
 | A carrier phase recovery circuit employs 16-phase switched-inverter-based harmonic-rejection complex mixers and low-latency QPSK phase detection circuits and achieves a wide bandwidth, making it ideal for energy-efficient coherent links in short-reach data center applications. A. E. Abdelrahman, M. G. Ahmed, M. A. Khalil, M. B. Younis, K. -S. Park and P. K. Hanumolu, "12.3 A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver," 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 1-3. | |
 | The temperature- and aging-compensated RC oscillator (TACO) counteracts the main oscillator's long-term drift by periodically aligning its frequency with a less-aged reference oscillator. Enhancements for TACO's long-term stability include utilizing resistors with higher activation energy, employing switched dual RC branches to alleviate stress from dc-current-induced electromigration (EM), and implementing duty cycling to reduce the aging rate of the reference oscillator. K. -S. Park et al., "A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C," in IEEE Journal of Solid-State Circuits, vol. 58, no. 12, pp. 3459-3469, Dec. 2023. | |
 | Enhancing the frequency stability of RC oscillators involves first- and second-order temperature compensation without requiring resistors with opposite temperature coefficients (TCs). Employing a three-point digital trim results in an inaccuracy of ±140 ppm, 83-ppm/V voltage sensitivity, and a 1.3-ppm Allan deviation floor. K. -S. Park et al., "A 1-μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/°C and Single-Point Trimmed 8.7-ppm/°C Stability From 40 °C to 95 °C," in IEEE Journal of Solid-State Circuits, vol. 58, no. 7, pp. 2064-2074, July 2023. | |
 | A clock generator achieves programmable, temperature-insensitive output frequencies by utilizing a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs). SAR logic accelerates FLL locking, while truncation error cancellation mitigates delta-sigma-induced jitter in FDIV. Y. Li et al., "A 20-μs Turn-On Time, 24-kHz Resolution, 1.5–100-MHz Digitally Programmable Temperature-Compensated Clock Generator," in IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp. 785-795, March 2023. | |
2022 | ||
 | A high-speed receiver designed for next-gen 8K ultra-HD TVs ensures error-free communication between the timing controller and display driver ICs. Challenges in implementing the receiver in a high-voltage process for co-integration with pixel drivers are overcome by including a level-shifting passive CTLE, a wideband active CTLE, a speculative DFE, an LDO with parallel error amplifiers, and a reference-less clock and data recovery circuit with a new frequency detector. T. Wang et al., "A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process," in IEEE Journal of Solid-State Circuits, vol. 57, no. 8, pp. 2521-2531, Aug. 2022. | |
 | The influence of resistor temperature coefficient (TC) on the accuracy of the RC oscillator's output frequency is alleviated by a parallel arrangement of two switched resistors, digitally controlled by pulse-density modulated sequences. Trimming at two temperatures gives an accuracy of 530 ppm (8.4 ppm/°C). A. Khashaba, J. Zhu, N. Pal, M. G. Ahmed and P. K. Hanumolu, "A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors," in IEEE Journal of Solid-State Circuits, vol. 57, no. 5, pp. 1470-1479, May 2022. | |
 | A ring oscillator (RO) based digital fractional-N frequency synthesizer incorporates a frequency doubler (FD), a 2-bit time-to-digital converter (TDC) with optimized thresholds, and a high-resolution digital-to-time converter (DTC) to minimize jitter. A piecewise linear function-based correction scheme improves DTC’s linearity, and on-chip digital calibration rectifies imperfections in the FD, TDC, and DTC. A. Elmallah, J. Zhu, A. Khashaba, K. M. Megawer, A. Elkholy and P. K. Hanumolu, "A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer," in IEEE Journal of Solid-State Circuits, vol. 57, no. 3, pp. 698-708, March 2022. | |
2021 | ||
 | A hybrid boost converter enhances the efficiency of LED drivers by combining a low-switching frequency time-interleaved series–parallel switched-capacitor (SC) stage with an inductive boost converter. Lower voltage-rated switches are employed, reducing switching losses significantly. Flying capacitors are softly charged with the boost stage's inductor to minimize charge-sharing losses in the SC stage. N. Pal et al., "A 91.15% Efficient 2.3–5-V Input 10–35-V Output Hybrid Boost Converter for LED-Driver Applications," in IEEE Journal of Solid-State Circuits, vol. 56, no. 11, pp. 3499-3510, Nov. 2021. | |
 | A low-power non-return-to-zero (NRZ) optical receiver integrates a low bandwidth trans-impedance amplifier (TIA) with duobinary sampling to enhance sensitivity at high data rates. Duobinary sampling utilizes the controlled TIA inter-symbol interference (ISI) to recover transmitted data efficiently, offering a hardware-efficient alternative to canceling ISI with a decision feedback equalizer. M. G. Ahmed, D. Kim, R. K. Nandwana, A. Elkholy, K. R. Lakshmikumar and P. K. Hanumolu, "A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling," in IEEE Journal of Solid-State Circuits, vol. 56, no. 9, pp. 2795-2803, Sept. 2021. | |
2020 | ||
 | A hybrid Dickson SC converter, with a 4:1 conversion ratio, supports a regulated output voltage of 0.3-0.9 V from a 3.4 to 4.2 V lithium-ion battery, delivering up to 1.5 A. Achieving a power density of 330 mW/mm2 and peak efficiency of 92.6%, it employs a segmented gate driver to enhance efficiency and reliability by minimizing low-voltage ringing. Integrated features include closed-loop output voltage regulation, dead-time control, and active capacitor-voltage balancing, optimizing active and passive device utilizations. P. Assem, W. -C. Liu, Y. Lei, P. K. Hanumolu and R. C. N. Pilawa-Podgurski, "Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 55, no. 9, pp. 2513-2528, Sept. 2020. | |
 | Achieving a 10 ns turn-on, a baud-rate ROO receiver employs a novel timing function compatible with a loop-unrolled decision feedback equalizer (DFE) for clock and data recovery. The rapid turn-on is achieved by adjusting the recovered clock phase through digitally controlled oscillator (DCO) frequency offsetting at each power-ON event. D. Kim, M. G. Ahmed, W. -S. Choi, A. Elkholy and P. K. Hanumolu, "A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 55, no. 8, pp. 2196-2205, Aug. 2020. | |
 | Multiple phases of the crystal oscillator (XO) are generated efficiently by employing a straightforward RC network between XO terminals. The combined edges create a clock at a multiple of the XO frequency, which is then utilized in an injection-locked clock multiplier to generate a low-noise, high-frequency output clock. Digital background calibration helps alleviate phase-spacing errors from process, voltage, temperature variations, and component mismatches. A. Khashaba, A. Elkholy, K. M. Megawer, M. G. Ahmed and P. K. Hanumolu, "A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques," in IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 592-601, March 2020. | |
2019 | ||
 | A fast-startup crystal oscillator employs a two-step injection technique, reducing startup time to 1.5× the theoretical minimum. Analysis of energy build-up in a crystal resonator guides optimal injection time based on desired steady-state amplitude and injection frequency error. Tolerable injection frequency error bounds for optimal timing are provided. K. M. Megawer et al., "A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection," in IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3257-3268, Dec. 2019. | |
 | A low-power RC relaxation oscillator attains minimal voltage and temperature sensitivities via a self-regulation loop, biasing the oscillator close to its zero-voltage coefficient point. T. Wang et al., "A 6 μ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz RC Oscillator Using Self-Regulation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 8, pp. 1297-1301, Aug. 2019. | |
 | Combining the advantages of RC relaxation oscillators (RCOs) and ring oscillators (ROs), a digital phase-locked loop (PLL) multiplies the frequency of an RC oscillator with an RO, achieving higher frequency, lower noise, and improved power efficiency. The type-II PLL utilizes a delay-modulating clock buffer for proportional control and a low-area digital-to-analog converter in the digitally controlled oscillator. J. Zhu, W. -S. Choi and P. K. Hanumolu, "A 0.016 mm2 0.26- $\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 8, pp. 2186-2194, Aug. 2019. | |
 | A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier utilizes a background-calibrated reference frequency doubler to enhance RO noise suppression bandwidth. It employs a digital frequency-tracking loop to continuously tune the oscillator's free-running frequency continuously, ensuring robust operation across variations. A least-mean-square algorithm accurately cancels deterministic jitter from input duty cycle errors. A. Elkholy, D. Coombs, R. K. Nandwana, A. Elmallah and P. K. Hanumolu, "A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler," in IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 2049-2058, July 2019. | |
 | A clock and data recovery (CDR) circuit operating below the baud rate recovers clock and data using only differential quarter-rate clocks. Eight samplers and an integrator collectively retrieve four data bits in each clock cycle. Four of these samplers are reused for phase detection and background calibration, enhancing the CDR's robustness to process voltage and temperature variations. D. Kim, W. -S. Choi, A. Elkholy, J. Kenney and P. K. Hanumolu, "A 15-Gb/s Sub-Baud-Rate Digital CDR," in IEEE Journal of Solid-State Circuits, vol. 54, no. 3, pp. 685-695, March 2019. | |
 | The crystal oscillator (XO) quadrupler produces low-noise output at four times the XO frequency without relying on a traditional phase-locked loop. Employing advanced digital correction techniques to address duty cycle errors and path mismatches, it generates a 216-MHz reference clock with an integrated jitter of 77 fsrms from a 54-MHz Pierce XO. K. M. Megawer, A. Elkholy, M. Ahmed, A. Elmallah and P. Hanumolu, "Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers," in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 65-74, Jan. 2019. | |
2018 | ||
 | A wide-range high high-resolution 2-stage digital-to-time converter (DTC) uses a counter in the first stage and a digitally controlled delay line in the second stage to decouple the range versus resolution trade-off. Background calibration corrects the interstage gain error. A. Elmallah, M. G. Ahmed, A. Elkholy, W. -S. Choi and P. K. Hanumolu, "A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, USA, 2018, pp. 1-4. | |
 | The rapid ON/OFF LC-based fractional-N injection-locked clock multiplier (ILCM) achieves fractional-N operation using a high-resolution digital-to-time converter for pulse alignment. An all-digital frequency-tracking loop continuously tunes the oscillator, enabling nearly instantaneous powering ON from OFF. Background calibration ensures robust operation across process, voltage, and temperature variations. A. Elkholy, A. Elmallah, M. G. Ahmed and P. K. Hanumolu, "A 6.75–8.25-GHz −250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier," in IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp. 1818-1829, June 2018. | |
 | A reconfigurable multi-output clock generator uses a digital phase-locked loop supplying a high-frequency clock to independent open-loop ΔΣ fractional dividers (FDIVs). A background-calibrated high-resolution digital-to-time converter ensures low-jitter performance regardless of process, voltage, and temperature variations. The FDIV operates over a wide frequency range and offers programmable spread spectrum modulation and instantaneous frequency switching. A. Elkholy, S. Saxena, G. Shu, A. Elshazly and P. K. Hanumolu, "Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers," in IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp. 1806-1817, June 2018. | |
 | A low-power source-synchronous multi-Gb/s transceiver aggressively scales supply voltage to minimize power consumption. The speed penalty associated with low-voltage operation is countered by multiplexing the transmitter and receiver synchronized with low-rate multi-phase clocks. Self-calibration corrects phase spacing errors caused by device mismatches. W. -S. Choi et al., "A 0.45–0.7 V 1–6 Gb/s 0.29–0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation," in IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 884-895, March 2018. | |
 | On-chip links designed for energy proportionality leverage architectural and circuit techniques to enhance energy efficiency across utilization levels. Employing single-ended signaling with a narrow pitch achieves a high throughput density. Fast-locking signaling and clocking circuits significantly reduce power-on time. D. Wei, T. Anand, G. Shu, J. E. Schutt-Ainé and P. K. Hanumolu, "A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects," in IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 873-883, March 2018. | |
 | Pulse frequency modulation (PFM) is integrated into time-based high switching frequency pulse-width modulation (PWM) dc-dc converters to enhance light load efficiency. Automatic and seamless switching between PWM and PFM modes ensures high efficiency, even with dynamic load variations. S. J. Kim, W. -S. Choi, R. Pilawa-Podgurski and P. K. Hanumolu, "A 10-MHz 2–800-mA 0.5–1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes," in IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 814-824, March 2018. | |
 | A high-sensitivity optical receiver employs a low-bandwidth shunt-feedback trans-impedance amplifier (SF-TIA) and a four-tap decision feedback equalizer to overcome the noise-bandwidth tradeoff. The SF-TIA features a high-gain multistage amplifier and a large feedback resistance, significantly improving noise performance. M. G. Ahmed et al., "A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 445-457, Feb. 2018. | |
2017 | ||
 | A clocking approach optimizes clock generation, recovery, and distribution in flexible-rate transceivers. It utilizes a low-jitter fixed-frequency clock from an integer-N PLL and locally generates/recovers fractional frequencies via multi-phase fractional-N clock multipliers. R. K. Nandwana et al., "A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS," 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017, pp. 492-493. | |
 | A hybrid switched-capacitor (SC) converter, employing a Dickson SC configuration alongside an LC output filter and PWM control, merges the benefits of SC and inductor-based converters, achieving high efficiency and power density across a continuous conversion range spanning from 4:1 to 15:1. W. -C. Liu, P. Assem, Y. Lei, P. K. Hanumolu and R. Pilawa-Podgurski, "A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS," 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017, pp. 182-183. | |
 | An oscillator uses a low-frequency, stable temperature clock generated by a low-power RC relaxation oscillator to improve the temperature stability of a low-noise ring oscillator. J. Zhu et al., "A 45–75MHz 197–452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS," 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2017, pp. 1-4. | |
 | A time-based gyrator efficiently implements active inductors using a ring oscillator for voltage integration and a switched transconductor for current injection. This approach provides inductive input impedance without requiring large resistors or capacitors. B. Salz et al., "A 0.7V time-based inductor for fully integrated low bandwidth filter applications," 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2017, pp. 1-4. | |
 | Utilizing a primarily digital architecture, a two-stage fractional-N phase-locked loop (PLL) integrates a first-order 1-bit ΔΣ frequency-to-digital converter. Enhancements include a fractional divider employing a phase interpolator, reducing phase quantizer input span, and multiplying delay-locked loop to increase its oversampling ratio. M. Talegaonkar et al., "A 5GHz Digital Fractional- $N$ PLL Using a 1-bit Delta–Sigma Frequency-to-Digital Converter in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2306-2320, Sept. 2017. | |
 | The energy efficiency of serial link transceivers is enhanced through strategies such as low-power clock generation, recovery, and distribution schemes, implementation of charge-based circuits for analog front-end and samplers/flip-flops, and utilization of a partially segmented voltage-mode (VM) output driver. The clock recovery unit employs a local ring oscillator-based PLL to minimize phase interpolators and high-frequency clock distribution. S. Saxena et al., "A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver," in IEEE Journal of Solid-State Circuits, vol. 52, no. 5, pp. 1399-1411, May 2017. | |
 | A digital PLL integrates a scrambling time-to-digital converter to enhance deterministic jitter performance and adopts a cascaded structure with a digital multiplying delay-locked loop as the first stage and a hybrid analog/digital PLL as the subsequent stage to attain low random jitter with low power consumption. R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram and P. K. Hanumolu, "A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 283-295, Feb. 2017. | |
 | Utilizing time-based control methods combines advantages from analog (no quantization error) and digital (compact area) PLLs. Integral control is achieved through a ring oscillator, tuning the oscillator frequency via a pulse-width modulated (PWM) signal. Pseudo-differential ring oscillators help mitigate unwanted PWM-induced spurious tones, ensuring favorable jitter performance. J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S. J. Kim and P. K. Hanumolu, "A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 8-20, Jan. 2017. | |
2016 | ||
 | A source-synchronous transceiver integrates dynamic voltage and frequency scaling, rapid on/off techniques, and robust supply voltage generation to achieve exceptional energy efficiency across various data rates. G. Shu et al., "A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS," 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2016, pp. 398-399. | |
 | A self-referenced VCO-based temperature sensor translates temperature into frequency and digital bits with minimal supply sensitivity. The sensing technique assesses temperature by comparing the output frequencies of two ring oscillators, each designed with distinct temperature sensitivities, eliminating the requirement for an external frequency reference. T. Anand, K. A. A. Makinwa and P. K. Hanumolu, "A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity," in IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2651-2663, Nov. 2016. | |
 | A digital fractional-N phase-locked loop (PLL) based on ring oscillators bridges the performance gap with LC-PLL by widening bandwidth through quantization noise cancellation and utilizing a dual-path digital loop filter to mitigate the adverse effects of digital-to-analog converter quantization noise. A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly and P. K. Hanumolu, "A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider," in IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. | |
 | A continuous-rate digital clock and data recovery system employs a conventional bang-bang phase detector (BBPD) for frequency acquisition. Utilizing a digitally controlled oscillator in the form of a ring-oscillator-based two-stage fractional-N PLL achieves a wide frequency range and low noise and resolves the tradeoff between jitter transfer bandwidth (JTRAN) and ring oscillator noise suppression. This design decouples JTRAN bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on BBPD gain. G. Shu et al., "A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition," in IEEE Journal of Solid-State Circuits, vol. 51, no. 2, pp. 428-439, Feb. 2016. | |
2015 | ||
 | A wide bandwidth VCO-based continuous-time ΔΣ modulator uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirements. K. Reddy, S. Dey, S. Rao, B. Young, P. Prabha and P. K. Hanumolu, "A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS," 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, Japan, 2015, pp. C256-C257. | |
 | A low-jitter, low-power LC-based injection-locked clock multiplier integrates a digital frequency-tracking loop, continuously tuning the oscillator's free-running frequency for robust operation across PVT variations. Precise theoretical large-signal analysis of injection-locked oscillators captures complexities like asymmetric lock-in range and the influence of frequency error on injection strength and phase noise performance. A. Elkholy, M. Talegaonkar, T. Anand and P. Hanumolu, "Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 3160-3174, Dec. 2015. | |
 | An embedded clock transceiver facilitates energy-proportional communication with swift on/off functionality. Methods for fast settling phase-locked loop, transmitter, receiver, and background phase calibration ensure instant synchronization upon power-on. T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly and P. K. Hanumolu, "A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 3101-3119, Dec. 2015 | |
 | A high switching frequency multi-phase buck converter employs a time-based compensator, combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID), to mitigate efficiency degradation from phase mismatch. This eliminates the need for complex current sensing, calibration circuitry, and high-resolution analog-to-digital converters for active and passive current sharing in analog and digital controllers. S. J. Kim, R. K. Nandwana, Q. Khan, R. C. N. Pilawa-Podgurski and P. K. Hanumolu, "A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2814-2824, Dec. 2015. | |
 | Utilizing the sensor's implicit capacitance, a current-to-digital converter achieves second-order noise shaping of quantization error through a passive integrator and a VCO-based quantizer. A loop incorporating a simple digital IIR filter addresses the VCO's voltage-to-frequency conversion non-linearity. P. Prabha et al., "A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications," in IEEE Journal of Solid-State Circuits, vol. 50, no. 8, pp. 1785-1795, Aug. 2015. | |
 | Control methods for high switching frequency buck converters employ time as the processing variable, operating with digital-like signals at CMOS levels without introducing quantization error. A ring oscillator used as an integrator replaces traditional opamp-RC or Gm-C integrators. A delay line handles voltage-to-time conversion and time signal summation. A basic flip-flop generates pulse-width modulated signals from the controller's time-based output. S. J. Kim et al., "High Frequency Buck Converter Design Using Time-Based Control Techniques," in IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 990-1001, April 2015. | |
 | Enhancing the phase noise performance of ring oscillator-based fractional-N PLLs, a hybrid phase/current-mode phase interpolator addresses the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. Combining phase detection and interpolation functions into an XOR phase detector/interpolator, precise quantization error cancellation is achieved without calibration. R. K. Nandwana et al., "A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method," in IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 882-895, April 2015. | |
 | Utilizing a high-resolution TDC and a truly fractional ΔΣ divider, a digital fractional-N PLL achieves low in-band noise and broad bandwidth. The fractional divider employs a digital-to-time converter to nullify ΔΣ quantization noise, reducing TDC dynamic range demands. A narrow-range, low-power time-amplifier-based TDC achieves sub-picosecond resolution, effectively mitigating limit cycle behavior and facilitating wide PLL bandwidth with rapid settling. A. Elkholy, T. Anand, W. -S. Choi, A. Elshazly and P. K. Hanumolu, "A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC," in IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 867-881, April 2015. | |
 | A full-rate burst-mode receiver achieves instantaneous phase-locking and input jitter filtering, crucial for energy-proportional links, by injecting input data edges into the oscillator within a traditional Type-II digital clock and data recovery circuit. Precise control over the number of injected data edges accurately manages both jitter transfer bandwidth and jitter tolerance corner. W. -S. Choi, T. Anand, G. Shu, A. Elshazly and P. K. Hanumolu, "A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links," in IEEE Journal of Solid-State Circuits, vol. 50, no. 3, pp. 737-748, March 2015. | |
2014 | ||
 | A high-sample-rate 3rd-order continuous-time ΔΣ modulator with wide bandwidth employs VCO-based integrators. It mitigates non-idealities introduced by VCOs at the modulator frontend through a combination of the circuit- and architecture-level techniques. B. Young, K. Reddy, S. Rao, A. Elshazly, T. Anand and P. K. Hanumolu, "A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators," 2014 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, USA, 2014, pp. 1-2. | |
 | Energy-proportional communication is facilitated by a rapid power-on transmitter architecture, incorporating a swift digital regulator, a fast-locking clock multiplier through precise frequency pre-setting and periodic reference insertion, and an enhanced edge replacement logic circuit. T. Anand, A. Elshazly, M. Talegaonkar, B. Young and P. K. Hanumolu, "A 5 Gb/s, 10 ns Power-On-Time, 36 $\mu$W Off-State Power, Fast Power-On Transmitter for Energy Proportional Links," in IEEE Journal of Solid-State Circuits, vol. 49, no. 10, pp. 2243-2258, Oct. 2014. | |
 | A burst-mode transmitter achieves a 6ns turn-on time through a fast frequency settling ring oscillator in a digital multiplying delay-locked loop and a swift on-off biasing scheme for the current mode output driver. The resistor tuning-based ring oscillator eliminates bias voltage-related settling time overhead. M. Talegaonkar, A. Elshazly, K. Reddy, P. Prabha, T. Anand and P. K. Hanumolu, "An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 49, no. 10, pp. 2228-2242, Oct. 2014. | |
 | Time-based transmit de-emphasis in voltage-mode drivers is achieved through two-level pulse-width modulation. This method effectively breaks the typical tradeoff between impedance matching, output swing, and de-emphasis resolution seen in conventional voltage-mode drivers that rely on voltage-based de-emphasis. S. Saxena, R. K. Nandwana and P. K. Hanumolu, "A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis," in IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1827-1836, Aug. 2014. | |
 | A high-resolution time-to-digital converter (TDC) employs switched-ring oscillators (SROs), utilizing oversampling and noise shaping to achieve precision without requiring calibration. Switching ring oscillators between two frequencies enables noise shaping of quantization error in an open-loop fashion. The SRO-TDC operates at high oversampling ratios by separating the sampling clock from input carrier frequencies. A. Elshazly, S. Rao, B. Young and P. K. Hanumolu, "A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques," in IEEE Journal of Solid-State Circuits, vol. 49, no. 5, pp. 1184-1197, May 2014. | |
 | A reference-less half-rate digital clock and data recovery (CDR) circuit features a phase-rotating phase-locked loop as a phase interpolator. It uses proportional control in the phase domain to decouple jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminating jitter peaking and removing JTRAN dependence on bang-bang phase detector gain. G. Shu et al., "A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop," in IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 1036-1047, April 2014. | |
 | A digital background calibration technique to realize a linear voltage-controlled-oscillator (VCO) based ADC. The distortion caused due to the VCO's nonlinear tuning characteristics is eliminated by introducing an inverse voltage-to-frequency transfer function in the signal path. The proposed calibration unit runs in the background and detects the inverse transfer function using a highly digital frequency locked loop. S. Rao, K. Reddy, B. Young and P. K. Hanumolu, "A Deterministic Digital Background Calibration Technique for VCO-Based ADCs," in IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 950-960, April 2014 | |
2013 | ||
 | A calibration-free digital multiplying delay-locked loop (MDLL) resolves the tradeoff between time-to-digital converter (TDC) resolution and oscillator phase noise in digital phase-locked loops (PLLs). Demonstrating reduced jitter accumulation to sub-picosecond levels and enhanced supply noise rejection, the MDLL outperforms conventional PLL architectures with lower power consumption. Comparison is made with a digital PLL utilizing a 1-bit TDC and a low-power regulator seeking improved supply noise immunity without increasing loop delay. A. Elshazly, R. Inti, B. Young and P. K. Hanumolu, "Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops," in IEEE Journal of Solid-State Circuits, vol. 48, no. 6, pp. 1416-1428, June 2013 | |
2012 | ||
 | A hysteretic buck converter utilizes hybrid voltage/current mode control to independently regulate output voltage and switching frequency. It maintains a constant switching frequency across various output voltages and inductor values, achieving low ripple and high efficiency. Q. Khan, A. Elshazly, S. Rao, R. Inti and P. K. Hanumolu, "A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control," 2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 2012, pp. 182-183. | |
 | Using basic CMOS inverters, ring oscillator integrators (ROIs) offer infinite DC gain at low supply voltages, impervious to transistor non-idealities or imperfections such as finite output impedance. Employing ROIs, a fourth-order filter maintains outstanding linearity even at a low 0.5V supply voltage. B. Drost, M. Talegaonkar and P. Hanumolu, "Analog Filter Design Using Ring Oscillator Integrators," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 3120-3129, Dec. 2012. | |
 | A continuous-time ΔΣ modulator integrates a VCO-based internal quantizer, employing a nonlinear VCO in a two-stage residue-canceling quantizer. It mitigates nonlinearity effects by operating within a limited region of the VCO's tuning curve. Placed in a continuous-time ΔΣ loop, it achieves second-order noise shaping with a first-order loop filter. K. Reddy et al., "A 16-mW 78-dB SNDR 10-MHz BW CT ΔΣ ADC Using Residue-Cancelling VCO-Based Quantizer," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2916-2927, Dec. 2012. | |
2011 | ||
 | A highly linear calibration-free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning the non-linearity of the VCO, does not require a multi-level feedback DAC, and eases anti-aliasing requirements. S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar and P. K. Hanumolu, "A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation," 2011 Symposium on VLSI Circuits - Digest of Technical Papers, Kyoto, Japan, 2011, pp. 270-271. | |
 | A digitally controlled Buck-Boost converter employs a fully synthesized constant ON/OFF time-based fractional-N controller to regulate the output across a 3.3V-to-5.5V input voltage range. It achieves this without needing a high-resolution digital pulse width modulator or an analog-to-digital converter. Q. Khan et al., "A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control," 2011 Proceedings of the ESSCIRC (ESSCIRC), Helsinki, Finland, 2011, pp. 439-442. | |
 | A feed-forward noise cancellation method enhances the power supply noise rejection of a low dropout regulator (LDO) when used with a conventional LDO, significantly extending the noise rejection bandwidth by almost an order of magnitude. B. Yang, B. Drost, S. Rao and P. K. Hanumolu, "A high-PSR LDO using a feedforward supply-noise cancellation technique," 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2011, pp. 1-4. | |
 | A digital clock and data recovery circuit integrates hybrid analog/digital phase detection for linear loop dynamics, eliminating the impact of nonlinearity and quantization error of a bang-bang detector. This architecture ensures constant jitter transfer bandwidth, reduces sensitivity to frequency quantization error, and decouples jitter generation from transfer characteristics. W. Yin, R. Inti, A. Elshazly, M. Talegaonkar, B. Young and P. K. Hanumolu, "A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery," in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 3163-3173, Dec. 2011. | |
 | A reference-less half-rate clock and data recovery circuit employs frequency dividers to create a sub-harmonic tone from incoming data. A digital frequency-locked loop synchronizes the oscillator to a multiple of the sub-harmonic tone. A conventional phase detector fine-tunesclock phases using early/late outputs, ensuring optimal receiver timing margins, even with uneven odd/even data widths. R. Inti, W. Yin, A. Elshazly, N. Sasidhar and P. K. Hanumolu, "A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance," in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 3150-3162, Dec. 2011. | |
 | A high-current LED driver employs an error-averaged, senseFET-based current sensing method for precise LED current regulation. The driver enhances efficiency and lowers costs by eliminating the conventional series current-regulation component. Operating in buck, buck-boost, and boost modes ensures high efficiency across the Li-Ion battery range (3-5.5 V). S. Rao et al., "A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique," in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2772-2783, Dec. 2011. | |
 | A digital phase-locked loop utilizes noise cancellation to counteract performance degradation from voltage noise in the ring oscillator supply. A deterministic test signal-based calibration ensures precise cancellation gain, adapting to various conditions. The hybrid control mechanism combines linear proportional and digital integral control, reducing jitter without requiring a high-resolution time-to-digital converter. A. Elshazly, R. Inti, W. Yin, B. Young, and P. Hanumolu, "A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration," in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2759-2771, Dec. 2011. | |
 | A hybrid phase-locked loop integrates linear proportional and double integral paths, along with bandwidth and tuning range tracking, enabled by a delta-sigma digital-to-analog converter. This configuration achieves low jitter, wide operating range, and low power consumption while addressing tradeoffs between bandwidth, tuning range, and frequency quantization error. W. Yin, R. Inti, A. Elshazly, B. Young and P. Hanumolu, "A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking," in IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1870-1880, Aug. 2011. | |
2010 | ||
 | A time-to-digital converter utilizes a phase-reference second-order continuous-time delta-sigma modulator to achieve high resolution and low power consumption. Operating on the input signal's phase, the modulator produces a noise-shaped one-bit output data stream, ensuring accurate time measurements. B. Young, S. Kwon, A. Elshazly and P. K. Hanumolu, "A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth," IEEE Custom Integrated Circuits Conference 2010, San Jose, CA, USA, 2010, pp. 1-4. | |