Our group primarily focuses our research on three specific areas:
Wireline Communication Circuits and Systems
It doesn’t matter how Big your data is if you can’t get it anywhere! Our group focuses on high-speed energy efficient clocking circuits for wireline systems. We seek to research and discover new architectures for high speed transceivers, clock-data recovery systems (CDRs), and frequency synthesizers. Traditional analog PLLs suffer large passive components that either dominate the noise-bandwidth or die area. Over the last few years, we have proposed numerous digital PLLs and injection-locked clock multipliers in order to push the noise and energy limits even lower. Significant work has also been done by the group in optimizing adaptive serial links in order to maintain low energy per bit across a wide range of data-rates. Similarly, we aim to create and discover new equalization schemes for high loss channels.
Time Based Signal Processing
Traditional signal processing can broadly be classified into several domains. We choose from either continuous or discrete time, and either analog or digital domains. In our group, we focus on a third domain: time based signal processing. Classic control building blocks (gain, integrator, sum) can all be constructed in the time domain using the same basic ideas found in a PLL. These components can be used to create new ultra-low power and area signal processing blocks such as filters, amplifiers, and more. Additionally, we research applications of time domain processing in other common circuits, such as data converters and and power management.
Power Management Circuits
Of course, none of the above would be possible without having power to allow the entire system to function. We specialize on time domain feedback systems for dc-dc converters in order to further increase efficiency. Similarly, the high energy efficiency demands of our serial link systems force us to develop faster and faster LDO’s to ensure that the power supply is not the limiting factor in our designs.